This invention relates to a packet switch device for transmission of (including exchange, communication, and forwarding, unless specifically limited) fixed length packets, which is applied in a broadband switch, a cross connect switch device, a router device, etc., and more particularly relates to an input buffer type packet switch device as one of the configuration methods of a large scale packet switch device.
In further details, this invention relates, as a packet switch device (an ATM switch device) that performs switching of fixed length packets called cells, to a packet switch device that enables efficient transmission of variable length packets such as IP (Internet Protocol) packets when they are input.
Along with the spread of the Internet in recent years, the IP data traffic (including voice information) in IP communications network systems is increasing at a great rate. In several years it's considered that IP traffic will become the major part of the communication traffic.
One element in this background is that, along with the progress of network technology, whose first example is bandwidth broadening of local area networks (LAN), and further examples in PC technology, such as the increasing functionality of personal computers (PCs) and speed increases of CPUs applied in PCs, it has become possible in practice to communicate not only data but also voice information between PCs across multiple LANs at high speeds.
Based on this, application software for executing voice communications, which conventionally were carried out by telephone, between PCs over the Internet constituted by leased lines, LANs, wide area networks (WANs), etc. and hardware which incorporates such software is being rapidly launched into the market. This system is a composite switching network system, or IP communications network system, which allows reduction of equipment and operations costs by integrating telephone networks and IP packet networks such as the Internet.
In a situation where, as described above, diversification and expansion of the communications network infrastructure is taking place, corporations are endeavoring to realize large-scale packet switch devices that are capable of transmitting IP packets in high volume and efficiency in order to cope with the ever-increasing volume of communication traffic.
IP packets are transmitted in the form of variable length packets. However, since strictly switching such variable length packets requires the processing of every byte, it is generally necessary to use a high-speed process, in which high-speed switching is difficult.
Therefore, in a technique to switch variable length packets at a high speed, variable length packets are divided in a similar manner as cells into 53-byte, fixed length packets on which fixed packet switching is performed inside the packet switch device. However, when sending data from the packet switch device, it is necessary to reconstruct such divided, fixed length packets into the variable length packets of original lengths to transmit them.
Here, two techniques of conventional packet switching devices are described with reference to FIG. 1, which shows forward variable length packets that are divided into fixed length packets.
(1) The scheduler part (not illustrated), at the input interface part (input INF) having an input buffer part, performs scheduling for each of the divided fixed length packets without considering the frames (variable length data constituted by a plurality of fixed length packets is scheduled without considering how the fixed length packets relate to the frames) and then inputs them to the packet switch (SW) as the common switch part. Furthermore, at the output buffer part provided for frame construction in the output interface part (output INF) in the stage after the packet switch (SW), the scheduler waits for the packets in order to construct the frames (refer to FIG. 1 (A)).
(2) The scheduler part (not illustrated), in the input interface part (input INF) having an input buffer part, considering the frames, performs successive scheduling packets constituting the same frame, and then inputs them into the packet switch (SW). Furthermore, after performing switching by the packet switch (SW) on the frame unit, it sends the frames to the output lines (output route) through the output interface part (output INF) (refer to FIG. 1 (B)).
In the technique (1) above, since the frames are not considered upon scheduling, scheduling is executed in each of the fixed length packets. Therefore, a pipeline process can be applied to perform scheduling advanced from the next cycle arranging scheduling processes in parallel, giving it an advantage of an increased processing speed. On the other hand, at the output interface part, packets are sent by the frame, which makes it necessary to temporarily store the fixed length packets from each of the input lines (input route) to construct the frames.
In a packet switch device adopting this technique, buffer memories, corresponding to the number of the input lines, are required for each of the output interface parts for constructing the frames. Therefore, a device having a large scale of switching requires a large quantity of output buffer memories.
On the other hand, with regard to technique (2) above, switching by the frame has an advantage of not requiring output buffer parts for the reconstruction of frames in the output interface parts. However, in order to realize scheduling by the frame, it is prohibited for other output lines to perform scheduling on an input line through which a frame is sent. Furthermore, once an input line is determined, it is required to perform scheduling continuously until sending of a frame is completed.
Therefore, upon scheduling, it is necessary to refer to the most up-to-date information as to which input line is currently sending a frame to which output line and it is not possible to perform advanced scheduling of the next cycle by arranging scheduling processes in parallel as in a pipeline process as describe above. As a result, a high speed scheduler part which executes scheduling of all lines within a unit of time is necessary, which is difficult to realize in a large scale packet switch device.